SiFive has released a high-end “P650” core for SoCs with up to 16 cores that includes the latest RISC-V hypervisor specification, one of 15 just released by RISC-V Int’l. In the meantime, Andes is speeding up its Linux-friendly AndesCore 45MP and NX27V cores.
Several RISC-V organizations have news to report in the run-up to next week’s RISC-V Summit in San Francisco. SiFive has unveiled a previously tested SiFive Performance P650 CPU core that is claimed to outperform Cortex-A77, the arm architecture used in the Snapdragon 865. The Linux-focused P650 supports the hypervisor extension, one of 15 new RISC-V specs released this week by. announced RISC-V International, the Switzerland-based organization that oversees RISC-V. Other Linux-related RISC-V news includes a performance improvement for Andes’ AndesCore 45MP and NX27V cores (see below).
Block diagram of the SiFive Performance P600 series
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This week, RISC-V International announced that membership had grown 130 percent in 2021. Also this week, Deloitte Global released a report (via TechRepublic) that predicts that sales of RISC-V processing cores will double in 2022 and double again in 2023 when they hit a $ 800 million market. The number is expected to approach $ 1 billion in 2024.
The report suggests that while the RISC-V market will continue to boom, driven in part by China’s interest in silicon independence and the lure of lower costs to smaller chip designers. However, large chipmakers and hardware makers are unlikely to be shedding their core investments from Arm and Intel anytime soon, says Deloitte.
Even SiFive’s new P650 lags behind the latest Intel and Arm designs, such as Qualcomm’s Snapdragon 8 Gen 1, announced this week. The smartphone SoC has the latest Armv9 cores, including the high-end Cortex-X2 (16 percent faster than -X1) as well as Cortex-A710 (10 percent faster than -A78) and Cortex-A510 (35 percent faster than -A78). A55). All Armv9 cores have at least twice the AI performance of their predecessors.
After all, Arm licensees may not switch to RISC-V as soon as planned if Nvidia’s $ 40 billion acquisition of Arm derails. This seems increasingly likely after the FTC was sued yesterday for blocking the deal.
Nonetheless, RISC-V continues to gain ground in areas like automotive and IoT, and the hypervisor specification and powerful CPU designs like the P650 should start to open up the data center market. RISC-V smartphones could hit the market next year. Sipeed, which recently launched a LicheeRV SBC that runs Linux on an Allwinner D1 RISC-V SoC, just posted a video showing a RISC-V RV64-powered smartphone prototype running Android 10.
SiFive Performance P650
The SiFive Performance P650 “is expected to be the fastest licensable RISC-V processor IP core on the market,” says SiFive. The Cortex-A77-like RISC-V CPU core design was developed for data center to edge, automotive, computing, mobile and more and is based on the Cortex-A55-like SiFive Performance P550 processor, which will be released in June Although Intel was unable to agree with SiFive on its purchase offer, the companies appear to continue as partners and Intel plans to use the P550 in an upcoming 7nm “Horse Creek” processor.
SiFive Performance P650 architecture
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The SiFive Performance P650, which like the P550 uses the latest U8 architecture from SiFive, “maintains an efficient core pipeline and at the same time expands the bandwidth of the processor instructions in order to achieve an impressive increase in performance of 40% per clock cycle,” claims SiFive in comparison to the P550. “Additional architectural improvements improve the maximum clock frequency and achieve an overall performance increase of 50% … with a projected score of 11+ SPECInt2006 / GHz.” The design “also retains a significant performance advantage per area” compared to the Cortex-A77, says SiFive.
Like the P550, the P650 uses the heterogeneous multi-core technology Arm Big.Little-like mix + match from SiFive. While the P550 is designed for up to quad-core SoCs, the P650 can drive 16-core SoCs.
Other highlights include an out-of-order pipeline with 4 issues and 13 phases versus 3 issues for the P550. The core offers private L2 caches and a streaming prefetcher for improved storage performance and supports up to 128 KB L1 and up to 4x 256-bit storage ports plus SECDED ECC. The design integrates SiFive WorldGuard security technology and supports cache stashing on L3 “for tightly coupled accelerators,” SiFive says.
The hypervisor specification optimizes RISC-V virtualization
The SiFive Performance P650 supports the new RISC-V hypervisor extension for virtualization. According to RISC-V International, the hypervisor specification “virtualizes the supervisor-level architecture to efficiently host guest operating systems on a Type 1 or Type 2 hypervisor.”
RISC-V International advises that hypervisors are not limited to the data center. Other applications include automotive and industrial control applications that require isolated hardware. KVM and other open source VMs have been ported “to simulators with the new specification,” according to the group.
A report from The Register states that the new hypervisor specification streamlines the “rather clunky” hardware virtualization support in RISC-V. “Hypervisors aware of this expansion can create virtualized environments for guests by allocating blocks of physical RAM within a virtual machine using pagination to RAM, which the guest operating system can divide into virtual memory areas where user-level programs can be run “Explains The Register. “This is far more flexible and beneficial in terms of the number of guests the hypervisor can juggle and managing the RAM usage of virtual machines, and arguably makes it easier to port hypervisors for other architectures to RISC-V. It also enables kernel-level hypervisors by virtualizing CPU control registers at the supervisor level and supporting bare metal hypervisors. “
The Register quotes SiFive vice president of product marketing, Chris Jones, as saying that the company expects the P650 to be used in 5nm-manufactured SoCs capable of clock speeds of 2.7 GHz or higher.
RISC-V International adds 15 RISC-V extensions
The hypervisor specification is just one of 15 new additions ratified by RISC-V International this week for up to 40 total additions. The other major new additions are the specifications for vector and scalar cryptography.
The Vector extension is the final version of the Vector (RVV) RV64GCV extensions, which are supported by several new Linux-enabled RISC-V processor designs, such as: B. the latest SiFive Intelligence X280. The specification “will help to speed up the computation of data-intensive processes such as ML inference for audio, image and speech processing,” says RISC-V International. The most important applications include “Edge computing applications from consumer IoT devices to industrial ML applications”.
The RISC-V Scalar Cryptography specification accelerates cryptographic workloads for small footprint deployments such as IoT and embedded devices. The enhancements “allow the implementation of standard cryptographic hash and block cipher algorithms that are in some cases an order of magnitude faster than using standard commands,” said Ben Marshall, Cryptographic Hardware Engineer at PQShield and a member of the RISC-V Technical Steering Committee. “In addition to the performance advantages, these new extensions can be implemented very cheaply, so that companies can integrate common cryptographic algorithms into even the smallest connected devices.”
Andes accelerates its Linux-powered A (X) 45MP and NX27V
Last December, Andes Technology introduced four new Linux-focused RISC-V cores, including the 32-bit A45MP and a 64-bit AX45MP that supports up to 4x cores at up to 2.4 GHz. Yesterday, Andes announced performance increases for these A (X) 45MP cores as well as a similar upgrade for its RV64GCV-enabled NX27V, which is based on the lower, Linux-enabled A27 series. (SiFive similarly announces performance upgrades from previously announced IPs, such as the 21G2 version of its Essential 7-series cores in July, including the Linux-enabled U74.)
AndesCore NX27V block diagram
Compared to the original A (X) 45MP cores, the upgraded models deliver “up to 3x memory bandwidth and at the same time increase floating-point performance by over 20 percent, measured against the Whetstone benchmark,” says Andes. “The latency for level 1 cache misses and level 2 cache hits has been cut in half,” which helps enable performance of 3.4 SPECint2006 / GHz, the company said. The upgrade also integrates the RISC-V-Trace interface and the debug specification.
The Edge AI-oriented NX27V has now been upgraded with full configurations from 128-bit to 512-bit VLEN / SIMD / MEM. For vector data types, the NX27V now implements FP16 to FP64 and Int8 to Int64 as well as the Andes-enhanced BF16 and Int4 for optimized AI data representations. With the full 512-bit configuration, the NX27V can “achieve over 98 times the speed of pure C programs and 66% higher performance for the MobileNet v1 benchmark than the pure 256-bit configuration,” says Andes.
The SiFive Performance P650 Architecture Preview will be offered to leading customers in the first quarter of 2022, with general availability starting mid-year. A development kit with RTL evaluation, Testbench RTL, SDK, FPGA bitstream and documentation will be available. For more information, see the SiFive announcement and the P650 product page.
For more information on the 15 new RISC-V enhancements, please visit the RISC-V International Announcements and Specifications page.
For more information on the Andes core accelerations, see the announcement.